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1 ltc1403-1/LTC1403A-1 14031f applicatio s u features descriptio u block diagra w serial 12-bit/14-bit, 2.8msps sampling adcs with shutdown n 2.8msps conversion rate n low power dissipation: 14mw n 3v single supply operation n 2.5v internal bandgap reference can be overdriven n 3-wire serial interface n sleep (10 m w) shutdown mode n nap (3mw) shutdown mode n 80db common mode rejection n 1.25v bipolar input range n tiny 10-lead mse package , ltc and lt are registered trademarks of linear technology corporation. n communications n data acquisition systems n uninterrupted power supplies n multiphase motor control n multiplexed data acquisition the ltc ? 1403-1/LTC1403A-1 are 12-bit/14-bit, 2.8msps serial adcs with differential inputs. the devices draw only 4.7ma from a single 3v supply and come in a tiny 10-lead mse package. a sleep shutdown feature lowers power consumption to 10 m w. the combination of speed, low power and tiny package makes the ltc1403-1/LTC1403A-1 suitable for high speed, portable applications. the 80db common mode rejection allows users to elimi- nate ground loops and common mode noise by measuring signals differentially from the source. the devices convert C1.25v to 1.25v bipolar inputs differ- entially. the absolute voltage swing for +a in and Ca in extends from ground to the supply voltage. the serial interface sends out the conversion results during the 16 clock cycles following conv - for compat- ibility with standard serial interfaces. if two additional clock cycles for acquisition time are allowed after the data stream in between conversions, the full sampling rate of 2.8msps can be achieved with a 50.4mhz clock. 14031 bd + 1 2 7 3 4 s & h gnd exposed pad LTC1403A-1 v ref 10 f a in a in + 14-bit adc 3v 10 f 14 14-bit latch 8 10 9 three- state serial output port 2.5v reference timing logic v dd sdo conv sck 5 6 11 thd, 2nd and 3rd vs input frequency for differential input signals frequency (mhz) 0.1 ?0 thd, 2nd, 3rd (db) ?4 ?8 ?2 ?6 1 10 100 14031 g19 ?6 ?2 ?8 ?04 ?0 ?4 thd 3rd 2nd
2 ltc1403-1/LTC1403A-1 14031f t jmax = 125 c, q ja = 150 c/ w exposed pad (pin 11) is gnd must be soldered to pcb 1 2 3 4 5 a in + a in v ref gnd gnd 10 9 8 7 6 conv sck sdo v dd gnd top view 11 mse package 10-lead plastic msop (notes 1, 2) supply voltage (v dd ) ................................................. 4v analog input voltage (note 3) ....................................C0.3v to (v dd + 0.3v) digital input voltage ................... C 0.3v to (v dd + 0.3v) digital output voltage .................. C 0.3v to (v dd + 0.3v) power dissipation .............................................. 100mw operation temperature range ltc1403c-1/ltc1403ac-1 ..................... 0 c to 70 c ltc1403i-1/ltc1403ai-1 .................. C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number mse part marking ltbgp ltbgq ltbgr ltbgs ltc1403cmse-1 ltc1403imse-1 ltc1403acmse-1 ltc1403aimse-1 the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. with internal reference. v dd = 3v ltc1403-1 LTC1403A-1 parameter conditions min typ max min typ max units resolution (no missing codes) l 12 14 bits integral linearity error (notes 4, 5, 18) l C2 0.25 2 C4 0.5 4 lsb offset error (notes 4, 18) l C10 1 10 C20 220 lsb gain error (note 4, 18) l C30 5 30 C60 10 60 lsb gain tempco internal reference (note 4) 15 15 ppm/ c external reference 1 1 ppm/ c the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 3v symbol parameter conditions min typ max units v in analog differential input range (notes 3, 8, 9) 2.7v v dd 3.3v l C1.25 to 1.25 v v cm analog common mode + differential 0 to v dd v input range (note 10) i in analog input leakage current l 1 m a c in analog input capacitance 13 pf t acq sample-and-hold acquisition time (note 6) l 39 ns t ap sample-and-hold aperture delay time 1 ns t jitter sample-and-hold aperture delay time jitter 0.3 ps cmrr analog input common mode rejection ratio f in = 1mhz, v in = 0v to 3v C60 db f in = 100mhz, v in = 0v to 3v C15 db consult ltc marketing for parts specified with wider operating temperature ranges. absolute axi u rati gs w ww u package/order i for atio uu w co verter characteristics u a alog i put u u
3 ltc1403-1/LTC1403A-1 14031f the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 3v. single-ended a in + signal drive with a in C = 1.5v dc. differential signal drive with v cm = 1.5v at a in + and a in C ltc1403-1 LTC1403A-1 symbol parameter conditions min typ max min typ max units sinad signal-to-noise plus 100khz input signal (note 19) 70.5 73.5 db distortion ratio 1.4mhz input signal (note 19) l 68 70.5 70 73.5 db 100khz input signal, external v ref = 3.3v, 72 76.3 db v dd 3 3.3v (note 19) 750khz input signal, external v ref = 3.3v, 72 76.3 db v dd 3 3.3v (note 19) thd total harmonic 100khz first 5 harmonics (note 19) C87 C90 db distortion 1.4mhz first 5 harmonics (note 19) l C83 C76 C86 C78 db sfdr spurious free 100khz input signal (note 19) C87 C90 db dynamic range 1.4mhz input signal (note 19) C83 C86 db imd intermodulation 0.625v p-p 1.4mhz summed with 0.625v p-p C82 C82 db distortion 1.56mhz into a in + and inverted into a in C code-to-code v ref = 2.5v (note 18) 0.25 1 lsb rms transition noise full power bandwidth v in = 2.5v p-p , sdo = 11585lsb p-p (note 15) 50 50 mhz full linear bandwidth s/(n + d) 3 68db 5 5 mhz the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 3v parameter conditions min typ max units v ref output voltage i out = 0 2.5 v v ref output tempco 15 ppm/ c v ref line regulation v dd = 2.7v to 3.6v, v ref = 2.5v 600 m v/v v ref output resistance load current = 0.5ma 0.2 w v ref settling time 2ms the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 3v symbol parameter conditions min typ max units v ih high level input voltage v dd = 3.3v l 2.4 v v il low level input voltage v dd = 2.7v l 0.6 v i in digital input current v in = 0v to v dd l 10 m a c in digital input capacitance (note 20) 5 pf v oh high level output voltage v dd = 3v, i out = C 200 m a l 2.5 2.9 v v ol low level output voltage v dd = 2.7v, i out = 160 m a 0.05 v v dd = 2.7v, i out = 1.6ma l 0.10 0.4 v i oz hi-z output leakage d out v out = 0v to v dd l 10 m a c oz hi-z output capacitance d out 1pf i source output short-circuit source current v out = 0v, v dd = 3v 20 ma i sink output short-circuit sink current v out = v dd = 3v 15 ma dy a ic accuracy u w i ter al refere ce characteristics uu u digital i puts a d digital outputs u u
4 ltc1403-1/LTC1403A-1 14031f symbol parameter conditions min typ max units f sample(max) maximum sampling frequency per channel l 2.8 mhz (conversion rate) t throughput minimum sampling period (conversion + acquisiton period) l 357 ns t sck clock period (note 16) l 19.8 10000 ns t conv conversion time (note 6) 16 18 sclk cycles t 1 minimum positive or negative sclk pulse width (note 6) 2 ns t 2 conv to sck setup time (notes 6, 10) 3 ns t 3 nearest sck edge before conv (note 6) 0 ns t 4 minimum positive or negative conv pulse width (note 6) 4 ns t 5 sck to sample mode (note 6) 4 ns t 6 conv to hold mode (notes 6, 11) 1.2 ns t 7 16th sck - to conv - interval (affects acquisition period) (notes 6, 7, 13) 45 ns t 8 minimum delay from sck to valid data (notes 6, 12) 8 ns t 9 sck to hi-z at sdo (notes 6, 12) 6 ns t 10 previous sdo bit remains valid after sck (notes 6, 12) 2 ns t 12 v ref settling time after sleep-to-wake transition (notes 6, 14) 2 ms ti i g characteristics w u the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 3v power require e ts w u the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 17) symbol parameter conditions min typ max units v dd supply voltage 2.7 3.6 v i dd positive supply voltage active mode l 4.7 7 ma nap mode l 1.1 1.5 ma sleep mode (ltc1403) 2 15 m a sleep mode (ltc1403a) 2 10 m a p d power dissipation active mode with sck in fixed state (hi or lo) 12 mw note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to gnd. note 3: when these pins are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below gnd or greater than v dd without latchup. note 4: offset and full-scale specifications are measured for a single- ended a in + input with a in C grounded and using the internal 2.5v reference. note 5: integral linearity is tested with an external 2.55v reference and is defined as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. the deviation is measured from the center of quantization band. note 6: guaranteed by design, not subject to test. note 7: recommended operating conditions. note 8: the analog input range is defined for the voltage difference between a in + and a in C . performance is specified with a in C = 1.5v dc while driving a in + . note 9: the absolute voltage at a in + and a in C must be within this range. note 10: if less than 3ns is allowed, the output data will appear one clock cycle later. it is best for conv to rise half a clock before sck, when running the clock at rated speed. note 11: not the same as aperture delay. aperture delay is smaller (1ns) because the 2.2ns delay through the sample-and-hold is subtracted from the conv to hold mode delay. note 12: the rising edge of sck is guaranteed to catch the data coming out into a storage latch. note 13: the time period for acquiring the input signal is started by the 16th rising clock and it is ended by the rising edge of convert. note 14: the internal reference settles in 2ms after it wakes up from sleep mode with one or more cycles at sck and a 10 m f capacitive load. note 15: the full power bandwidth is the frequency where the output code swing drops to 3db with a 2.5v p-p input sine wave. note 16: maximum clock period guarantees analog performance during conversion. output data can be read without an arbitrarily long clock. note 17: v dd = 3v, f sample = 2.8msps. note 18: the LTC1403A-1 is measured and specified with 14-bit resolution (1lsb = 152 m v) and the ltc1403-1 is measured and specified with 12-bit resolution (1lsb = 610 m v). note 19: full-scale sinewaves are fed into the noninverting input while the inverting input is kept at 1.5v dc. note 20: the sampling capacitor at each input accounts for 4.1pf of the input capacitance.
5 ltc1403-1/LTC1403A-1 14031f enobs and sinad vs input frequency sfdr vs input frequency t a = 25 c, v dd = 3v. single ended a in + signal drive with a in C = 1.5v dc, differential signals drive both inputs with v cm = 1.5v dc (LTC1403A-1) thd, 2nd and 3rd vs input frequency typical perfor a ce characteristics uw snr vs input frequency frequency (mhz) 0.1 10.0 enobs (bits) sinad (db) 11.0 12.0 1 10 100 14031 g01 9.0 9.5 10.5 11.5 8.5 8.0 62 68 74 56 59 65 71 53 50 frequency (mhz) 0.1 ?0 thd, 2nd, 3rd (db) ?4 ?8 ?2 ?6 1 10 100 14031 g02 ?6 ?2 ?8 ?04 ?0 ?4 thd 3rd 2nd frequency (mhz) 0.1 68 sfdr (db) 56 44 1 10 100 14031 g03 80 74 62 50 86 92 98 104 frequency (mhz) 0.1 62 snr (db) 56 50 1 10 100 14031 g04 68 65 59 53 71 74 enobs and sinad vs input frequency for differential input signals thd, 2nd and 3rd vs input frequency for differential input signals frequency (mhz) 0.1 10.0 enobs (bits) sinad (db) 11.0 12.0 1 10 100 14031 g18 9.0 9.5 10.5 11.5 8.5 8.0 62 68 74 56 59 65 71 53 50 frequency (mhz) 0.1 ?0 thd, 2nd, 3rd (db) ?4 ?8 ?2 ?6 1 10 100 14031 g19 ?6 ?2 ?8 ?04 ?0 ?4 thd 3rd 2nd 1.3mhz sine wave 4096 point fft plot 98khz sine wave 4096 point fft plot frequency (hz) magnitude (db) ?0 ?0 ?0 14031 g05 ?0 ?0 ?20 ?00 0 ?0 ?0 ?0 ?0 ?10 0 700k 350 1.05m 1.4m frequency (hz) 0 magnitude (db) ?0 ?0 ?0 14031 g06 ?0 ?0 ?20 350k 1.05m 700k 1.4m ?00 0 ?0 ?0 ?0 ?0 ?10 sfdr vs input frequency for differential input signals frequency (mhz) 0.1 68 sfdr (db) 56 44 1 10 100 14031 g20 80 74 62 50 86 92 98 104
6 ltc1403-1/LTC1403A-1 14031f t a = 25 c, v dd = 3v. single ended a in + signal drive with a in C = 1.5v dc, differential signals drive both inputs with v cm = 1.5v dc (LTC1403A-1) typical perfor a ce characteristics uw differential and integral linearity vs conversion rate sinad vs conversion rate conversion rate (msps) 2 2.25 3 2.5 3.75 4 2.75 3.25 linearity (lsb) 14031 g10 8 7 6 5 4 3 2 1 0 ? ? ? ? max inl 18 clocks per conversion max dnl min dnl min inl 3.5 conversion rate (msps) 2 2.25 3.25 2.75 4 3 2.5 3.75 3.5 s/(n+d) (db) 14031 g11 78 77 76 75 74 73 72 71 70 69 68 external v ref = 3.3v f in ~ f s /3 external v ref = 3.3v f in ~ f s /40 internal v ref = 2.5v f in ~ f s /3 internal v ref = 2.5v f in ~ f s /40 1.4mhz input summed with 1.56mhz input imd 4096 point fft plot for differential input signals frequency (hz) 0 magnitude (db) ?0 ?0 ?0 14031 g07 ?0 ?0 ?20 800k 200k 400k 600k 1m 1.2m 1.4m ?00 0 ?0 ?0 ?0 ?0 ?10 differential linearity vs output code integral linearity vs output code output code 0 ?.0 differential linearity (lsb) ?.8 ?.4 ?.2 0 1.0 0.4 4096 8192 14031 g08 ?.6 0.6 0.8 0.2 12288 16384 output code 0 ? integral linearity (lsb) ? ? 0 4 1 4096 8192 14071 g09 ? 2 3 12288 16384 frequency (hz) magnitude (db) ?0 ?0 ?0 14031 g21 ?0 ?0 ?20 ?00 0 ?0 ?0 ?0 ?0 ?10 0 700k 350 1.05m 1.4m frequency (hz) magnitude (db) ?0 ?0 ?0 14031 g22 ?0 ?0 ?20 ?00 0 ?0 ?0 ?0 ?0 ?10 0 700k 350 1.05m 1.4m 1.3mhz sine wave 4096 point fft plot for differential input signals 10.7mhz sine wave 4096 point fft plot for differential input signals output code 0 ? integral linearity (lsb) ? ? 0 4 1 4096 8192 14071 g23 ? 2 3 12288 16384 integral linearity vs output code for differential input signals
7 ltc1403-1/LTC1403A-1 14031f reference voltage vs load current reference voltage vs v dd v dd supply current vs conversion rate 2.5v p-p power bandwidth cmrr vs frequency psrr vs frequency t a = 25 c, v dd = 3v (ltc1403-1 and LTC1403A-1) frequency (hz) 1m 10m 100m 1g ?8 amplitude (db) ?2 ? 0 14031 g12 ?4 ?0 ?6 6 12 frequency (hz) 100 cmrr (db) 0 ?0 ?0 ?0 ?0 ?00 ?20 1k 10k 100k 1m 14031 g13 10m 100m frequency (hz) 110 ?0 psrr (db) ?5 ?0 ?5 ?0 100 1k 10k 100k 1m 14031 g14 ?5 ?0 ?5 ?0 ?5 load current (ma) 0.4 0.8 1.2 1.6 14031 g15 2.0 0.2 0 0.6 1.0 1.4 1.8 2.4890 v ref (v) 2.4894 2.4898 2.4902 2.4892 2.4896 2.4900 v dd (v) 2.4890 v ref (v) 2.4894 2.4898 2.4902 2.4892 2.4896 2.4900 2.8 3.0 3.2 3.4 14031 g16 2.6 3.6 conversion rate (msps) 0 2.0 1.6 1.2 0.8 0.4 2.8 3.2 2.4 3.6 4.0 v dd supply current (ma) 14031 g17 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 typical perfor a ce characteristics uw
8 ltc1403-1/LTC1403A-1 14031f a in + (pin 1): noninverting analog input. a in + operates fully differentially with respect to a in C with a C1.25v to 1.25v differential swing with respect to a in C and a 0v to v dd common mode swing. a in C (pin 2): inverting analog input. a in C operates fully differentially with respect to a in + with a 1.25v to C1.25v differential swing with respect to a in + and a 0v to v dd common mode swing. v ref (pin 3): 2.5v internal reference. bypass to gnd and to a solid analog ground plane with a 10 m f ceramic capacitor (or 10 m f tantalum in parallel with 0.1 m f ce- ramic). can be overdriven by an external reference be- tween 2.55v and v dd . gnd (pins 4, 5, 6, 11): ground and exposed pad. these ground pins and the exposed pad must be tied directly to the solid ground plane under the part. keep in mind that analog signal currents and digital output signal currents flow through these pins. v dd (pin 7): 3v positive supply. this single power pin supplies 3v to the entire chip. bypass to gnd and to a solid analog ground plane with a 10 m f ceramic capacitor (or 10 m f tantalum in parallel with 0.1 m f ceramic). keep in mind that internal analog currents and digital output signal currents flow through this pin. care should be taken to place the 0.1 m f bypass capacitor as close to pins 6 and 7 as possible. sdo (pin 8): three-state serial data output. each of output data words represents the difference between a in + and a in C analog inputs at the start of the previous conversion. the output format is 2s complement. sck (pin 9): external clock input. advances the conver- sion process and sequences the output data on the rising edge. responds to ttl ( 3v) and 3v cmos levels. one or more pulses wake from sleep. conv (pin 10): convert start. holds the analog input signal and starts the conversion on the rising edge. responds to ttl ( 3v) and 3v cmos levels. two pulses with sck in fixed high or fixed low state start nap mode. four or more pulses with sck in fixed high or fixed low state start sleep mode. uu u pi fu ctio s block diagra w 14031 bd + 1 2 7 3 4 s & h gnd exposed pad LTC1403A-1 v ref 10 f a in a in + 14-bit adc 3v 10 f 14 14-bit latch 8 10 9 three- state serial output port 2.5v reference timing logic v dd sdo conv sck 5 6 11
9 ltc1403-1/LTC1403A-1 14031f nap mode and sleep mode waveforms sck to sdo delay slk conv nap sleep v ref t 1 t 12 t 1 note: nap and sleep are internal signals 14031 td02 t 8 t 10 sck sdo 14031 td03 v ih v oh v ol t 9 sck sdo v ih 90% 10% sck conv internal s/h status sdo t 7 t 3 t 1 1 18 17 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 t 2 t 6 t 8 t 4 t 5 t 8 t 9 t acq sample hold hold hi-z hi-z t conv 14-bit data word sdo represents the analog input from the previous conversion *bits marked "x" after d0 should be ignored. t throughput 14031 td01 d11 d10 d8 d7 d6 d5 d4 d3 d2 d1 d0 x* x* d9 sample 1 ltc1403 timing diagram ltc1403a timing diagram sck conv internal s/h status sdo t 7 t 3 t 1 1 18 17 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 t 2 t 6 t 8 t 4 t 5 t 8 t 9 t acq sample hold hold hi-z hi-z t conv 14-bit data word sdo represents the analog input from the previous conversion t throughput 14031 td01b d13 d12 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d11 sample 1 ti i g diagra u ww
10 ltc1403-1/LTC1403A-1 14031f driving the analog input the differential analog inputs of the ltc1403-1/LTC1403A-1 are easy to drive. the inputs may be driven differentially or as a single-ended input (i.e., the a in C input is set to v cm ). both differential analog inputs, a in + with a in C , are sampled at the same instant. any unwanted signal that is common to both inputs of each input pair will be reduced by the common mode rejection of the sample-and-hold circuit. the inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. during conversion, the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low, then the ltc1403-1/ LTC1403A-1 inputs can be driven directly. as source imped- ance increases, so will acquisition time. for minimum acqui- sition time with high source impedance, a buffer amplifier must be used. the main requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 39ns for full throughput rate). also keep in mind while choosing an input amplifier, the amount of noise and har- monic distortion added by the amplifier. choosing an input amplifier choosing an input amplifier is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the amplifier from charging the sam- pling capacitor, choose an amplifier that has a low output impedance (<100 w ) at the closed-loop bandwidth frequency. for example, if an amplifier is used with a gain of 1 and has a unity-gain bandwidth of 50mhz, then the output impedance at 50mhz must be less than 100 w . the second requirement is that the closed-loop bandwidth must be greater than 40mhz to ensure adequate small-signal settling for full throughput rate. if slower op amps are used, more time for settling can be provided by increasing the time between conversions. the best choice for an op amp to drive the ltc1403-1/LTC1403A-1 will depend on the application. gen- erally, applications fall into two categories: ac applications where dynamic specifications are most critical and time domain applications where dc accuracy and settling time are most critical. the following list is a summary of the op amps that are suitable for driving the ltc1403-1/LTC1403A-1. (more detailed information is available in the linear technol- ogy databooks and our website at www.linear.com.) ltc ? 1566-1: low noise 2.3mhz continuous time low- pass filter. lt1630: dual 30mhz rail-to-rail voltage fb amplifier. 2.7v to 15v supplies. very high a vol , 500 m v offset and 520ns settling to 0.5lsb for a 4v swing. thd and noise are C93db to 40khz and below 1lsb to 320khz (a v = 1, 2v p-p into 1k w , v s = 5v), making the part excellent for ac applications (to 1/3 nyquist) where rail-to-rail performance is desired. quad version is available as lt1631. lt1632: dual 45mhz rail-to-rail voltage fb amplifier. 2.7v to 15v supplies. very high a vol , 1.5mv offset and 400ns settling to 0.5lsb for a 4v swing. it is suitable for applica- tions with a single 5v supply. thd and noise are C93db to 40khz and below 1lsb to 800khz (a v = 1, 2v p-p into 1k w , v s = 5v), making the part excellent for ac applications where rail-to-rail performance is desired. quad version is available as lt1633. lt1813: dual 100mhz 750v/ m s 3ma voltage feedback amplifier. 5v to 5v supplies. distortion is C86db to 100khz and C77db to 1mhz with 5v supplies (2v p-p into 500 w ). excellent part for fast ac applications with 5v supplies. lt1801: 80mhz gbwp, C75dbc at 500khz, 2ma/amplifier, 8.5nv/ ? hz. lt1806/lt1807: 325mhz gbwp, C80dbc distortion at 5mhz, unity-gain stable, r-r in and out, 10ma/amplifier, 3.5nv/ ? hz. lt1810: 180mhz gbwp, C90dbc distortion at 5mhz, unity-gain stable, r-r in and out, 15ma/amplifier, 16nv/ ? hz. lt1818/lt1819: 400mhz, 2500v/ m s,9ma, single/dual volt- age mode operational amplifier. lt6200: 165mhz gbwp, C85dbc distortion at 1mhz, unity- gain stable, r-r in and out, 15ma/amplifier, 0.95nv/ ? hz. lt6203: 100mhz gbwp, C80dbc distortion at 1mhz, unity-gain stable, r-r in and out, 3ma/amplifier, 1.9nv/ ? hz. lt6600-10: amplifier/filter differential in/out with 10mhz cutoff. applicatio s i for atio wu u u
11 ltc1403-1/LTC1403A-1 14031f input filtering and source impedance the noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the ltc1403 -1/LTC1403A-1 noise and distortion. the small-signal bandwidth of the sample-and-hold circuit is 50mhz. any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is sufficient for many applications. for example, figure 1 shows a 47pf capacitor from a in + to ground and a 51 w source resistor to limit the input bandwidth to 47mhz. the 47pf capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the adc input from sampling-glitch sensitive circuitry. high quality ca- pacitors and resistors should be used since these compo- nents can add distortion. npo and silvermica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. when high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole filter is required. high external source resis- tance, combined with the 13pf of input capacitance, will reduce the rated 50mhz bandwidth and increase acquisi- tion time beyond 39ns. figure 1. rc input filter the 1.25v range is also ideally suited for ac-coupled signals in single supply applications. figure 2 shows how to ac couple signals in a single supply system without needing a mid-supply 1.5v external reference. the dc common mode level is supplied by the previous stage that is already bounded by the single supply voltage of the system. the common mode range of the inputs extend from ground to the supply voltage v dd . if the difference between the a in + and a in C inputs exceeds 1.25v, the output code will stay fixed at zero and all ones and if this difference goes below C1.25v, the output code will stay fixed at one and all zeros. applicatio s i for atio wu u u 10 f v cm 1.5v dc 11 3 a in ltc1403-1/ LTC1403A-1 a in + 47pf 2 1 51 gnd v ref 1403a f01 + a in + c4 10 f 14031 f02 r2 1.6k c2 1 f c1 1 f c1, c2: film type c3: cog type c4: ceramic bypass r1 1.6k 1 2 3 ltc1403-1/ LTC1403A-1 a in v ref r3 51 c3 56pf v in figure 2. ac coupling of ac signals with 1khz low cut input range the analog inputs of the ltc1403 -1/LTC1403A-1 may be driven fully differentially with a single supply. each input may swing up to 3v p-p individually. in the conversion range, each input is always up to 1.25v more positive or more negative than the inverting input of each channel. internal reference the ltc1403 -1/LTC1403A-1 has an on-chip, temperature compensated, bandgap reference that is factory trimmed near 2.5v to obtain 1.25v input span. the reference amplifier output v ref , (pin 3) must be bypassed with a capacitor to ground. the reference amplifier is stable with capacitors of 1 m f or greater. for the best noise perfor- mance, a 10 m f ceramic or a 10 m f tantalum in parallel with a 0.1 m f ceramic is recommended. the v ref pin can be overdriven with an external reference as shown in fig- ure 3. the voltage of the external reference must be higher than the 2.5v of the class a pull-up output of the internal figure 3 gnd ltc1403-1/ LTC1403A-1 v ref 10 f 11 3 3v ref 14031 f03
12 ltc1403-1/LTC1403A-1 14031f reference. the recommended range for an external refer- ence is 2.55v to v dd . an external reference at 2.55v will see a dc quiescent load of 0.75ma and as much as 3ma during conversion. input span versus reference voltage the differential input range has a unipolar voltage span that equals the difference between the voltage at the reference buffer output v ref at pin 3, and the voltage at the ground (exposed pad ground). the differential input range of the adc is 1.25v when using the internal reference. the internal adc is referenced to these two nodes. this relationship also holds true with an external reference. differential inputs the ltc1403 -1/LTC1403A-1 have a unique differential sample-and-hold circuit that allows inputs from ground to v dd . the adc will always convert the bipolar difference of a in + C a in C , independent of the common mode voltage at the inputs. the common mode rejection holds up at extremely high frequencies, see figure 4. the only require- ment is that both inputs not go below ground or exceed v dd . integral nonlinearity errors (inl) and differential nonlinearity errors (dnl) are largely independent of the common mode voltage. however, the offset error will vary. the change in offset error is typically less than 0.1% of the common mode voltage. figure 5 shows the ideal input/output characteristics for the ltc1403 -1/LTC1403A-1. the code transitions occur midway between successive integer lsb values (i.e., 0.5lsb, 1.5lsb, 2.5lsb, fs C 1.5lsb). the output code is natural binary with 1lsb = 2.5v/16384 = 153 m v for the LTC1403A-1, and 1lsb = 2.5v/4096 = 610 m v for the ltc1403-1. the LTC1403A-1 has 1lsb rms of random white noise. figure 6a shows the ltc1819 converting a single ended input signal to differential input signals for optimum thd and sfdr performance as shown in the fft plot (figure 6b). applicatio s i for atio wu u u figure 4 cmrr vs frequency frequency (hz) 100 cmrr (db) 0 ?0 ?0 ?0 ?0 ?00 ?20 1k 10k 100k 1m 14031 f04 10m 100m figure 5 ltc1403-1/LTC1403A-1 transfer characteristic input voltage (v) 2? complement output code 14031 f05 011...111 011...110 011...101 100...000 100...001 100...010 fs ?1lsb ?s a in LTC1403A-1 a in + c1 47pf to 1000pf 1 r1 51 c3 1 f c5 0.1 f 5v ?v c4 1 f r5 1k 1.5v cm r3 499 r4 499 r6 1k c2 47pf to 1000pf r2 51 c6 0.1 f v in 1.25v p-p max 1403a f06a + u1 1/2 lt1819 + u2 1/2 lt1819 figure 6a. the lt1819 driving the LTC1403A-1 differentially
13 ltc1403-1/LTC1403A-1 14031f board layout and bypassing wire wrap boards are not recommended for high resolu- tion and/or high speed a/d converters. to obtain the best performance from the ltc1403 -1/LTC1403A-1, a printed circuit board with ground plane is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particu- lar, care should be taken not to run any digital track alongside an analog signal track. if optimum phase match between the inputs is desired, the length of the two input wires should be kept matched. high quality tantalum and ceramic bypass capacitors should be used at the v dd and v ref pins as shown in the block diagram on the first page of this data sheet. for optimum performance, a 10 m f surface mount avx capaci- tor with a 0.1 m f ceramic is recommended for the v dd and v ref pins. alternatively, 10 m f ceramic chip capacitors such as murata grm219r60j106m may be used. the capacitors must be located as close to the pins as possible. the traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. figure 7 shows the recommended system ground connec- tions. all analog circuitry grounds should be terminated at the ltc1403 -1/LTC1403A-1 gnd (pins 4, 5, 6 and ex- posed pad). the ground return from the ltc1403-1/ LTC1403A-1 (pins 4, 5, 6 and exposed pad) to the power supply should be low impedance for noise free operation. digital circuitry grounds must be connected to the digital supply common. in applications where the adc data outputs and control signals are connected to a continu- ously active microprocessor bus, it is possible to get errors in the conversion results. these errors are due to feedthrough from the microprocessor to the successive approximation comparator. the problem can be elimi- nated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to iso- late the adc data bus. power-down modes upon power-up, the ltc1403 -1/LTC1403A-1 is initialized to the active state and is ready for conversion. the nap and sleep mode waveforms show the power-down modes for the ltc1403 -1/LTC1403A-1. the sck and conv inputs control the power-down modes (see timing diagrams). two rising edges at conv, without any intervening rising edges at sck, put the ltc1403 -1/LTC1403A-1 in nap applicatio s i for atio wu u u figure 7. recommended layout 14031 f07 frequency (hz) magnitude (db) ?0 ?0 ?0 14031 f06b ?0 ?0 ?20 ?00 0 ?0 ?0 ?0 ?0 ?10 0 371k 185k 556k 741k figure 6b. ltc1403-1 6mhz sine wave 4096 point fft plot with the lt1819 driving the inputs differentially
14 ltc1403-1/LTC1403A-1 14031f mode and the power drain drops from 14mw to 6mw. the internal reference remains powered in nap mode. one or more rising edges at sck wake up the ltc1403-1/ LTC1403A-1 for service very quickly, and conv can start an accurate conversion within a clock cycle. four rising edges at conv, without any intervening rising edges at sck, put the ltc1403 -1/LTC1403A-1 in sleep mode and the power drain drops from 16mw to 10 m w. one or more rising edges at sck wake up the ltc1403 -1/LTC1403A-1 for operation. the internal reference (v ref ) takes 2ms to slew and settle with a 10 m f load. note that, using sleep mode more frequently than every 2ms, compromises the settled accuracy of the internal reference. note that, for slower conversion rates, the nap and sleep modes can be used for substantial reductions in power consumption. digital interface the ltc1403 -1/LTC1403A-1 has a 3-wire spi (serial protocol interface) interface. the sck and conv inputs and sdo output implement this interface. the sck and conv inputs accept swings from 3v logic and are ttl compatible, if the logic swing does not exceed v dd . a detailed description of the three serial port signals follows: conversion start input (conv) the rising edge of conv starts a conversion, but subse- quent rising edges at conv are ignored by the ltc1403-1/ LTC1403A-1 until the following 16 sck rising edges have occurred. it is necessary to have a minimum of 16 rising edges of the clock input sck between rising edges of conv. but to obtain maximum conversion speed, it is necessary to allow two more clock periods between con- versions to allow 39ns of acquisition time for the internal adc sample-and-hold circuit. with 16 clock periods per conversion, the maximum conversion rate is limited to 2.8msps to allow 39ns for acquisition time. in either case, the output data stream comes out within the first 16 clock periods to ensure compatibility with processor serial ports. the duty cycle of conv can be arbitrarily chosen to be used as a frame sync signal for the processor serial port. a simple approach to generate conv is to create a pulse that is one sck wide to drive the ltc1403-1/ LTC1403A-1 and then buffer this signal with the appropri- ate number of inverters to ensure the correct delay driving the frame sync input of the processor serial port. it is good practice to drive the ltc1403 -1/LTC1403A-1 conv input first to avoid digital noise interference during the sample- to-hold transition triggered by conv at the start of conver- sion. it is also good practice to keep the width of the low portion of the conv signal greater than 15ns to avoid introducing glitches in the front end of the adc just before the sample-and-hold goes into hold mode at the rising edge of conv. minimizing jitter on the conv input in high speed applications where high amplitude sinewaves above 100khz are sampled, the conv signal must have as little jitter as possible (10ps or less). the square wave output of a common crystal clock module usually meets this requirement easily. the challenge is to generate a conv signal from this crystal clock without jitter corrup- tion from other digital circuits in the system. a clock divider and any gates in the signal path from the crystal clock to the conv input should not share the same integrated circuit with other parts of the system. as shown in the interface circuit examples, the sck and conv inputs should be driven first, with digital buffers used to drive the serial port interface. also note that the master clock in the dsp may already be corrupted with jitter, even if it comes directly from the dsp crystal. another problem with high speed processor clocks is that they often use a low cost, low speed crystal (i.e., 10mhz) to generate a fast, but jittery, phase-locked-loop system clock (i.e., 40mhz). the jitter in these pll-generated high speed clocks can be several nanoseconds. note that if you choose to use the frame sync signal generated by the dsp port, this signal will have the same jitter of the dsps master clock. serial clock input (sck) the rising edge of sck advances the conversion process and also udpates each bit in the sdo data stream. after conv rises, the third rising edge of sck starts clocking out the 12/14 data bits with the msb sent first. a simple approach is to generate sck to drive the ltc1403-1/ LTC1403A-1 first and then buffer this signal with the appropriate number of inverters to drive the serial clock input of the processor serial port. use the falling edge of the clock to latch data from the serial data output (sdo) applicatio s i for atio wu u u
15 ltc1403-1/LTC1403A-1 14031f into your processor serial port. the 14-bit serial data will be received right justified, in a 16-bit word with 16 or more clocks per frame sync. it is good practice to drive the ltc1403 -1/LTC1403A-1 sck input first to avoid digital noise interference during the internal bit comparison decision by the internal high speed comparator. unlike the conv input, the sck input is not sensitive to jitter because the input signal is already sampled and held constant. serial data output (sdo) upon power-up, the sdo output is automatically reset to the high impedance state. the sdo output remains in high impedance until a new conversion is started. sdo sends out 12/14 bits in 2s complement format in the output data stream beginning at the third rising edge of sck after the rising edge of conv. sdo is always in high impedance mode when it is not sending out data bits. please note the delay specification from sck to a valid sdo. sdo is always guaranteed to be valid by the next rising edge of sck. the 16-bit output data stream is compatible with the 16-bit or 32-bit serial port of most processors. hardware interface to tms320c54x the ltc1403 -1/LTC1403A-1 is a serial output adc whose interface has been designed for high speed buffered serial ports in fast digital signal processors (dsps). figure 8 shows an example of this interface using a tms320c54x. the buffered serial port in the tms320c54x has direct access to a 2kb segment of memory. the adcs serial data can be collected in two alternating 1kb segments, in real time, at the full 2.8msps conversion rate of the ltc1403-1/ LTC1403A-1. the dsp assembly code sets frame sync mode at the bfsr pin to accept an external positive going pulse and the serial clock at the bclkr pin to accept an external positive edge clock. buffers near the ltc1403-1/ LTC1403A-1 may be added to drive long tracks to the dsp to prevent corruption of the signal to ltc1403-1/ LTC1403A-1. this configuration is adequate to traverse a typical system board, but source resistors at the buffer outputs and termination resistors at the dsp, may be needed to match the characteristic impedance of very long transmission lines. if you need to terminate the sdo transmission line, buffer it first with one or two 74actxx gates. the ttl threshold inputs of the dsp port respond properly to the 3v swing from the sdo pin. applicatio s i for atio wu u u figure 8. dsp serial interface to tms320c54x 14031 f08 7 10 9 8 6 3-wire serial interfacelink v dd conv sck ltc1403-1/ LTC1403A-1 sdo v cc bfsr bclkr tms320c54x bdr gnd conv 0v to 3v logic swing clk 3v 5v b13 b12
16 ltc1403-1/LTC1403A-1 14031f applicatio s i for atio wu u u ; 10-23-03 ****************************************************************** ; files: 014si.asm -> 1403 bipolar sine wave collection with serial port interface ; bvectors.asm buffered mode. ; s2k14ini.asm 2k buffer size. ; first element at 1024, last element at 1023, two middles at 2047 and 0000 ; bipolar mode ; works 16 or 64 clock frames. ; negative edge bclkr ; negative bfsr pulse ; -0 data shifted ; 1' cable from counter to conv at dut ; 2' cable from counter to clk at dut ; *************************************************************************** .width 160 .length 110 .title sineb0 bsp in auto buffer mode .mmregs .setsect .text, 0x500,0 ;set address of executable .setsect vectors, 0x180,0 ;set address of incoming 1403 data .setsect buffer, 0x800,0 ;set address of bsp buffer for clearing .setsect result, 0x1800,0 ;set address of result for clearing .text ;.text marks start of code start: ;this label seems necessary ;make sure /pwrdwn is low at j1-9 ;to turn off ac01 adc tim=#0fh prd=#0fh tcr = #10h ; stop timer tspc = #0h ; stop tdm serial port to ac01 pmst = #01a0h ; set up iptr. processor mode status register sp = #0700h ; init stack pointer. dp = #0 ; data page ar2 = #1800h ; pointer to computed receive buffer. ar3 = #0800h ; pointer to buffered serial port receive buffer ar4 = #0h ; reset record counter call sineinit ; double clutch the initialization to insure a proper sinepeek: call sineinit ; reset. the external frame sync must occur 2.5 clocks ; or more after the port comes out of reset. wait goto wait ; buffered receive interrupt routine breceive: ifr = #10h ; clear interrupt flags tc = bitf(@bspce,#4000h) ; check which half (bspce(bit14)) of buffer if (ntc) goto bufull ; if this still the first half get next half bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15)) return_enable ; mask and shift input data bufull: b = *ar3+ << -0 ; load acc b with bsp buffer and shift right -0 b = #03fffh & b ; mask out the tristate bits with #03fffh b = b ^ #2000h ; invert the msb for bipolar operation b *ar2+ = data(#0bh) ; store b to out buffer and advance ar2 pointer tc = (@ar2 == #02000h) ; output buffer is 2k starting at 1800h if (tc) goto start ; restart if out buffer is at 1fffh goto bufull
17 ltc1403-1/LTC1403A-1 14031f applicatio s i for atio wu u u ; dummy bsend return bsend return_enable ;this is also a dummy return to define bsend ;in vector table file bvectors.asm ; end isr .copy c:\dskplus\1403\s2k14ini.asm ;initialize buffered serial port .space 16*32 ;clear a chunk at the end to mark the end ;====================================================================== ; ; vectors ; ;====================================================================== .sect vectors ;the vectors start here .copy c:\dskplus\1403\bvectors.asm ;get bsp vectors .sect buffer ;set address of bsp buffer for clearing .space 16*0x800 .sect result ;set address of result for clearing .space 16*0x800 .end ; *************************************************************************** ; file: bvectors.asm -> vector table for the c54x dskplus 10.jul.96 ; bsp vectors and debugger vectors ; tdm vectors just return ; *************************************************************************** ; the vectors in this table can be configured for processing external and ; internal software interrupts. the dskplus debugger uses four interrupt ; vectors. these are reset, trap2, int2, and hpiint. ; * do not modify these four vectors if you plan to use the debugger * ; ; all other vector locations are free to use. when programming always be sure ; the hpiint bit is unmasked (imr=200h) to allow the communications kernel and ; host pc interact. int2 should normally be masked (imr(bit 2) = 0) so that the ; dsp will not interrupt itself during a hint. hint is tied to int2 externally. ; ; ; .title vector table .mmregs reset goto #80h ;00; reset * do not modify if using debugger * nop nop nmi return_enable ;04; non-maskable external interrupt nop nop nop trap2 goto #88h ;08; trap2 * do not modify if using debugger * nop nop .space 52*16 ;0c-3f: vectors for software interrupts 18-30 int0 return_enable ;40; external interrupt int0 nop nop nop int1 return_enable ;44; external interrupt int1 nop nop nop
18 ltc1403-1/LTC1403A-1 14031f applicatio s i for atio wu u u int2 return_enable ;48; external interrupt int2 nop nop nop tint return_enable ;4c; internal timer interrupt nop nop nop brint goto breceive ;50; bsp receive interrupt nop nop nop bxint goto bsend ;54; bsp transmit interrupt nop nop nop trint return_enable ;58; tdm receive interrupt nop nop nop txint return_enable ;5c; tdm transmit interrupt nop nop int3 return_enable ;60; external interrupt int3 nop nop nop hpiint dgoto #0e4h ;64; hpiint * do not modify if using debugger * nop nop .space 24*16 ;68-7f; reserved area ********************************************************************** * (c) copyright texas instruments, inc. 1996 * ********************************************************************** * * * file: s2k14ini.asm bsp initialization code for the c54x dskplus * * for use with 1403 in buffered mode * * bspc and spc are the same in the c542 * * bspce and spce seem the same in the c542 * ********************************************************************** .title buffered serial port initialization routine on .set 1 off .set !on yes .set 1 no .set !yes bit_8 .set 2 bit_10 .set 1 bit_12 .set 3 bit_16 .set 0 go .set 0x80 ********************************************************************** * this is an example of how to initialize the buffered serial port (bsp). * the bsp is initialized to require an external clk and fsx for * operation. the data format is 16-bits, burst mode, with autobuffering * enabled. *
19 ltc1403-1/LTC1403A-1 14031f applicatio s i for atio wu u u ***************************************************************************************************** *ltc1403 timing from board with 10mhz crystal. * *10mhz, divided from 40mhz, forced to clkin by 1403 board. * *horizontal scale is 25ns/chr or 100ns period at bclkr * *timing measured at dsp pins. jxx pin labels for jumper cable. * *bfsr pin j1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/~~~~~~~~~~~* *bclkr pin j1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~* *bdr pin j1-26 ____> 1)|((format & 2)<<1)|(burstmode <<3)|(intclk <<4)|(intsync <<5)) ,spcval .eval ((clkdiv)|(fs_polarity <<5)|(clk_polarity<<6)|((format & 1)<<7)|(frame_ignore<<8)|(pcm_mode<<9)), spceval .eval (spceval|(xmtautobuf<<10)|(xmthalt<<12)|(rcvautobuf<<13)|(rcvhalt<<15)), spceval sineinit: bspc = #spcval ; places buffered serial port in reset ifr = #10h ; clear interrupt flags imr = #210h ; enable hpint,enable brint0 intm = 0 ; all unmasked interrupts are enabled. bspce = #spceval ; programs bspce and abu axr = #xmtbufaddr ; initializes transmit buffer start address bkx = #xmtbufsize ; initializes transmit buffer size arr = #rcvbufaddr ; initializes receive buffer start address bkr = #rcvbufsize ; initializes receive buffer size bspc = #(spcval | go) ; bring buffered serial port out of reset return ;for transmit and receive because go=0xc0 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20 ltc1403-1/LTC1403A-1 14031f lt/tp 0404 1k ? printed in usa ? linear technology corporation 2004 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts mse package 10-lead plastic msop (reference ltc dwg # 05-08-1663) u package descriptio part number description comments adcs ltc1608 16-bit, 500ksps parallel adc 5v supply, 2.5v span, 90db sinad ltc1604 16-bit, 333ksps parallel adc 5v supply, 2.5v span, 90db sinad ltc1609 16-bit, 250ksps serial adc 5v, configurable bipolar/unipolar inputs ltc1411 14-bit, 2.5msps parallel adc 5v, selectable spans, 80db sinad ltc1414 14-bit, 2.2msps parallel adc 5v supply, 2.5v span, 78db sinad ltc1403/ltc1403a 12-/14-bit, 2.8msps serial adc 3v, 15mw unipolar inputs, msop package ltc1407/ltc1407a 12-/14-bit, 3msps simultaneous sampling adc 3v, 2-channel differential, unipolar inputs, 14mw, msop package ltc1407-1/ltc1407a-1 12-/14-bit, 3msps simultaneous sampling adc 3v, 2-channel differential, bipolar inputs, 14mw, msop package ltc1420 12-bit, 10msps parallel adc 5v, selectable spans, 72db sinad ltc1405 12-bit, 5msps parallel adc 5v, selectable spans, 115mw ltc1412 12-bit, 3msps parallel adc 5v supply, 2.5v span, 72db sinad ltc1402 12-bit, 2.2msps serial adc 5v or 5v supply, 4.096v or 2.5v span ltc1864/ltc1865 16-bit, 250ksps serial adc 5v supply, 1 and 2 channel, 4.3mw, msop package dacs ltc1666/ltc1667/ltc1668 12-/14-/16-bit, 50msps dacs 87db sfdr, 20ns settling time ltc1592 16-bit, serial softspan tm i out dac 1lsb inl/dnl, software selectable spans references lt1790-2.5 micropower series reference in sot-23 0.05% initial accuracy, 10ppm drift lt1461-2.5 precision voltage reference 0.04% initial accuracy, 3ppm drift lt1460-2.5 micropower series voltage reference 0.1% initial accuracy, 10ppm drift softspan is a trademark of linear technology corporation. msop (mse) 0603 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 0.27 (.007 ?.011) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 2.083 0.102 (.082 .004) 2.794 0.102 (.110 .004) 0.50 (.0197) bsc 10 1 bottom view of exposed pad option 1.83 0.102 (.072 .004) 2.06 0.102 (.081 .004)

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